1. Field of the Invention
The present invention relates to a semiconductor device that uses a MOS capacitor having the voltage dependence as a phase compensation circuit element of an operational amplifier or the like.
2. Description of Related Art
In a conventional semiconductor device, when a MOS capacitor is used for the phase compensation of an operational amplifier or the like, two MOS capacitors are connected in parallel with their respective terminals of opposite polarities connected to each other. The MOS capacitor is formed in a semiconductor substrate and configured by disposing an insulating film (gate oxide film) between a gate electrode and a diffusion layer. In the following, a “CMOS operational amplifier” disclosed in JP 10 (1998)-270957 A will be described as a conventional example of the semiconductor device with reference to FIG. 7.
In FIG. 7, an N-channel MOS transistor 87 and an N-channel MOS transistor 88 constitute a differential input stage, and signals from an inverting input terminal 81 and a non-inverting input terminal 82 are input to the gates of the MOS transistors 87 and 88, respectively. The source of the MOS transistor 87 and the source of the MOS transistor 88 are connected to each other, and a constant current is drawn through the drain of an N-channel MOS transistor 89. In the MOS transistor 89, a drain current is set by a voltage applied to a bias voltage input terminal 83.
The sources of P-channel MOS transistors 91, 92 are connected to a common power supply terminal 84 (higher potential power supply VDD). The drain of the MOS transistor 87 is connected to the gates of the MOS transistors 91, 92, and also to the drain of the MOS transistor 91. The drain of the MOS transistor 88 is connected to the drain of the MOS transistor 92.
The drain of the MOS transistor 88 is connected further to the gate of a P-channel MOS transistor 93, whose source is connected to the higher potential power supply VDD, and also to one terminal of a phase compensation capacitor 86. The other terminal of the phase compensation capacitor 86 is connected to the drain of the MOS transistor 93. The drain of the MOS transistor 93 is connected to the drain of an N-channel MOS transistor 90 in which a drain current is set by the voltage applied to the bias voltage input terminal 83. The node between the drains of the MOS transistors 93 and 90 is connected to an output terminal 85.
The phase compensation capacitor 86 includes two MOS capacitors 94, 95 that are connected in parallel with their respective terminals of opposite polarities connected to each other. FIG. 8 shows a cross-sectional structure of the MOS capacitors 94, 95 that serve as MOS-type capacitative elements (N well capacitative elements).
In FIG. 8, reference numeral 114 denotes a P-type semiconductor substrate in which N well layers (N-type diffusion layers having a low impurity concentration) 111, 112 and a field oxide film 113 are formed. N-type diffusion layers having a high impurity concentration (N-type diffusion layers with a small specific resistance) 107, 108 and 109, 110 are formed in the N well layers 111 and 112, respectively. A gate electrode 103 is disposed via a gate oxide film 105 in a region between the N-type diffusion layers 107 and 108. Similarly, a gate electrode 104 is disposed via a gate oxide film 106 in a region between the N-type diffusion layers 109 and 110. Terminals 101, 102 are provided for the MOS capacitors 95, 94.
The terminal 101 of the MOS capacitor 95 and the terminal 102 of the MOS capacitor 94 are connected to the gate and the drain of the MOS transistor 93 in FIG. 7, respectively.
With this configuration, when a voltage V1 i.e., the voltage of the terminal 101 of the MOS capacitor 95) is higher than a voltage VOUT (i.e., the voltage of the terminal 102 of the MOS capacitor 94), a depletion layer is formed in the N well layer 111 directly below the gate electrode 103 in the MOS capacitor 95, and the capacitance of the MOS capacitor 95 becomes extremely small. On the other hand, when the voltage V1 is lower than the voltage VOUT, a depletion layer is formed in the N well layer 112 directly below the gate electrode 104 in the MOS capacitor 94, and the capacitance of the MOS capacitor 94 becomes extremely small.
However, since the MOS capacitors 95, 94 are connected in parallel with their respective terminals of opposite polarities connected to each other, whether the voltage V1 is higher or lower than the voltage VOUT by a certain level (except for the vicinity of the same potential), the capacitance of one of the MOS capacitors is maintained at a predetermined level, namely is not reduced due to the depletion layer. That is, whether the voltage V1 is higher or lower than the voltage VOUT by a certain level (except for the vicinity of the same potential), the capacitance of the phase compensation capacitor 86 (i.e., the total capacitance of the MOS capacitors 94, 95) is maintained at a predetermined value or more. Therefore, when the semiconductor device is used as an operational amplifier or the like, it will not oscillate.
In addition to JP 10 (1998)-270957 A, JP 11 (1999)-97626 A also discloses a similar example in which a parasitic capacitance component is added using AL wiring.
However, the conventional semiconductor device as shown in FIGS. 7 and 8 has the following problems.
FIG. 9 is a characteristic diagram showing the voltage dependence of the phase compensation capacitor 86. The horizontal axis indicates a voltage (VOUT-V1), and the vertical axis indicates a capacitance. A dotted-line curve a represents the capacitance of the MOS capacitor 94, a broken-line curve b represents the capacitance of the MOS capacitor 95, and a solid-line curve c represents the capacitance of the phase compensation capacitor 86 (i.e., the total capacitance of the MOS capacitors 94, 95).
In a general MOS capacitor, if the voltage of a diffusion layer terminal is higher than that of a gate electrode terminal, a depletion layer is formed in the N well layer directly below the gate electrode. Consequently, the length L as the capacitor in combination with the thickness of the gate oxide film is increased to reduce the capacitance. The characteristics of the MOS capacitor 94, the characteristics of the MOS capacitor 95, and the capacitance of the phase compensation capacitor 86 (i.e., the total capacitance of the MOS capacitors 94, 95) are as indicated by the curves a, b, and c in FIG. 9, nothing that a small variation of the voltage dependence of the MOS capacitor may be caused according to the conditions of the impurity concentration of the N well layer, the thickness of the gate oxide film, or the like.
As shown in FIG. 9, when (VOUT-V1) is in the vicinity of 0 V, the capacitance of the phase compensation capacitor 86 is extremely small. Thus, if the operational amplifier in FIG. 7 is used, e.g., in such a way that the voltage between the terminals of the phase compensation capacitor 86 changes with the input conditions, the operational amplifier probably will oscillate under the operating conditions in which (VOUT-V1) is in the vicinity of 0 V.
To eliminate the possibility of oscillation even under the operating conditions in which (VOUT-V1) is in the vicinity of 0 V, the phase compensation capacitor 86 has to be very large, leading to an increase in the chip size.